
`include "common_header.verilog"

//  *************************************************************************
//  File : rx_ff_length.v
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized Reproduction or Use is Expressly Prohibited. 
//  Copyright (c) 2001 MoreThanIP.com, Germany
//  Designed by : Francois Balay
//  fbalay@morethanip.com
//  *************************************************************************                   
//  Decription : Receive FIFO Frame Length Calculation
//  Version    : $Id: rx_ff_length.v,v 1.1 2008/03/27 16:42:26 mr Exp $
//  *************************************************************************

module rx_ff_length (
   
   clk,
   clk_ena,
   reset,
   rx_sop_int,
   rx_eop_int,
   rx_wren_int,
   frm_length);
   
   
input   clk;                    //  Local Receive Clock
input   clk_ena;                //  Local Receive Clock Enable
input   reset;                  //  Global Reset
input   rx_sop_int;             //  Start of Packet
input   rx_eop_int;             //  End of Packet
input   rx_wren_int;            //  Data FIFO Read Enable
output  [13:0] frm_length;      //  Frame Length
wire    [13:0] frm_length; 
reg     [13:0] frm_length_int; 

always @(posedge reset or posedge clk)
   begin : process_1
   if (reset == 1'b 1)
      begin
      frm_length_int <= {14{1'b 0}};	
      end
   else
      begin
      if (clk_ena == 1'b 1)
         begin
//  Length Reset - Start of Packet
//  ------------------------------
         if (rx_wren_int == 1'b 1 & rx_sop_int == 1'b 1)
            begin
            frm_length_int <= 14'd 1;
            end
         else if (rx_wren_int == 1'b 1 & rx_eop_int == 1'b 0 )
            begin
            frm_length_int <= frm_length_int + 14'd 1;	
            end
         end
      end
   end

assign frm_length = frm_length_int; 

endmodule // module rx_ff_length

